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freescale semiconductor data sheet document number: msc8113 rev. 1, 12/2008 ? freescale semiconductor, inc., 2008. all rights reserved. msc8113 fc-pbga?431 20 mm 20 mm ? three starcore? sc140 dsp extended cores, each with an sc140 dsp core, 224 kbyte of internal sram m1 memory (1436 kbyte total), 16 way 16 kbyte instruction cache (icache), four-entry write buffer, external cache support, programmable interrupt controller (pic), local interrupt controller (lic), and low-power wait and stop processing modes. ? 475 kbyte m2 memory for critical data and temporary data buffering. ? 4 kbyte boot rom. ? m2-accessible multi-core mqbus connecting the m2 memory with all three cores, operating at the core frequency, with data bus access of up to 128-bit reads and up to 64-bit writes, central efficient round-robin arbiter for core access to the bus, and atomic operation control of m2 memory access by the cores and the local bus. ? internal pll configured are reset by configuration signal values. ? 60x-compatible system bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by an external host to internal resources, slave support with direct access to internal resources including m1 and m2 memories, and on-device arbitration for up to four master devices. ? direct slave interface (dsi) using a 32/64-bit slave host interface with 21?25 bit addressing and 32/64-bit data transfers, direct access by an external host to internal and external resources, synchronous or asynchronous accesses with burst capability in synchronous mode, dual or single strobe mode, write and read buffers to improve host bandwidth, byte enable signals for 1/2/4/8-byte write granularity, sliding window mode for access using a reduced number of address pins, chip id decoding to allow one cs signal to control multiple dsps, broadcast mode to write to multiple dsps, and big-endian/little-endian/munged support. ? three mode signal multiplexing: 64-bit dsi and 32-bit system bus, 32-bit dsi and 64-bit system bus, or 32-bit dsi and 32-bit system bus, and ethernet port (mii/rmii). ? flexible memory controller with three upms, a gpcm, a page-mode sdram machine, glueless interface to a variety of memories and devices, byte enables for 64- or 32-bit bus widths, 8 memory banks for external memories, and 2 memory banks for ipbus peripherals and internal memories. ? multi-channel dma controller with 16 time-multiplexed single channels, up to four external peripherals, done or drack protocol for two external peripherals,.service for up to 16 internal requests from up to 8 internal fifos per channel, fifo generated watermarks and hungry requests, priority-based time-multiplexing between channels using 16 internal priority levels or round-robin time-multiplexing between channels, flexible channel configuration with connection to local bus or system bus, and flyby transfer support that bypasses the fifo. ? up to four independent tdm modules with programmable word size (2, 4, 8, or 16-bit), hardware-base a-law/ -law conversion, up to 128 mbps data rate for all channels, with glueless interface to e1 or t1 framers, and can interface with h-mvip/h.110 devices, tsi, and codecs such as ac-97. ? ethernet controller with support for 10/100 mbps mii/rmii/smii including full- and half-duplex operation, full-duplex flow controls, out-of-sequence transmit queues, programmable maximum frame length including jumbo frames and vlan tags and priority, retransmission after collision, crc generation and verification of inbound/outbound packets, address recognition (including exact match, broadcast address, individual hash check, group hash check, and promiscuous mode), pattern matching, insertion with expansion or replacement for transmit frames, vlan tag insertion, rmon statistic s, local bus master dma for descriptor fetching and buffer access, and optional multiplexing with gpio (mii/rmii/smii) or dsi/system bus signals lines (mii/rmii). ? uart with full-duplex operation up to 6.25 mbps. ? up to 32 general-purpose input/output (gpio) ports. ?i 2 c interface that allows booting from eeprom devices. ? two timer modules, each with sixteen configurable 16-bit timers. ? eight programmable hardware semaphores. ? global interrupt controller (gic) with interrupt consolidation and routing to int_out , nmi_out , and the cores; twenty-four virtual maskable interrupts (8 per core) and three virtual nmi (one per core) that can be generated by a simple write access. ? optional booting external memory, external host, uart, tdm, or i 2 c. tri-core digital signal processor because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 2 table of contents 1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 fc-pbga ball layout diagrams. . . . . . . . . . . . . . . . . . .4 1.2 signal list by ball location. . . . . . . . . . . . . . . . . . . . . . .7 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2 recommended operating conditions. . . . . . . . . . . . . .14 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .14 2.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . .14 2.5 ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3 hardware design considerations . . . . . . . . . . . . . . . . . . . . . .38 3.1 start-up sequencing recommendations . . . . . . . . . . .38 3.2 power supply design considerations. . . . . . . . . . . . . .38 3.3 connectivity guidelines . . . . . . . . . . . . . . . . . . . . . . . .39 3.4 external sdram selection . . . . . . . . . . . . . . . . . . . . . .40 3.5 thermal considerations . . . . . . . . . . . . . . . . . . . . . . . .41 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6 product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 list of figures figure 1. msc8113 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2. starcore ? sc140 dsp extended core block diagram . 3 figure 3. msc8113 package, top view. . . . . . . . . . . . . . . . . . . . . 5 figure 4. msc8113 package, bottom view . . . . . . . . . . . . . . . . . . 6 figure 5. overshoot/undershoot voltage for v ih and v il . . . . . . . 15 figure 6. start-up sequence: v dd and v ddh raised together . . 16 figure 7. start-up sequence: v dd raised before v ddh with clkin started with v ddh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. power-up sequence for v ddh and v dd /v ccsyn . . . . . 17 figure 9. timing diagram for a reset configuration write . . . . . 21 figure 10.internal tick spacing for memory controller signals. . . 21 figure 11.siu timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 12.clkout and clkin signals. . . . . . . . . . . . . . . . . . . . . 25 figure 13.dma signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 14.asynchronous single- and dual-strobe modes read timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15.asynchronous single- and dual-strobe modes write timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 16.asynchronous broadcast write timing diagram . . . . . . 28 figure 17.dsi synchronous mode signals timing diagram . . . . . 30 figure 18.tdm inputs signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19.tdm output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 20.uart input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21.uart output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 22.timer timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 23.mdio timing relationship to mdc . . . . . . . . . . . . . . . . 33 figure 24.mii mode signal timing . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 25.rmii mode signal timing . . . . . . . . . . . . . . . . . . . . . . . 34 figure 26.smii mode signal timing. . . . . . . . . . . . . . . . . . . . . . . . 35 figure 27.gpio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 28.ee pin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 29.test clock input timing diagram. . . . . . . . . . . . . . . . . . 37 figure 30.boundary scan (jtag) timing diagram . . . . . . . . . . . . 37 figure 31.test access port timing diagram . . . . . . . . . . . . . . . . . 37 figure 32.trst timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 33.core power supply decoupling. . . . . . . . . . . . . . . . . . . 38 figure 34.v ccsyn bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 35.msc8113 mechanical information, 431-pin fc-pbga package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 3 figure 1. msc8113 block diagram figure 2. starcore ? sc140 dsp extended core block diagram mqbus sqbus local bus 128 128 boot rom 64 pll jtag rs-232 internal local bus internal system bus ipbus ip master 64 64 uart memory controller m2 ram gpio pins interrupts memory controller system bus 32/64 dsi port 32 32/64 pll/clock jtag port sc140 extended core sc140 extended core sc140 extended core system interface 32 timers 4 tdms dma bridge siu registers direct slave interface (dsi) 8 hardware semaphores gic gpio mii/rmii/smii ethernet sc140 power management core program sequencer address register file data alu register file address alu eonce jtag xa xb p qbus irqs irqs mqbus sqbus local bus 128 128 64 64 64 lic pic 128 128 qbus interface instruction cache m1 ram notes: 1. the arrows show the data transfer direction. qbus bank 1 qbus bank 3 2 . the qbus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four qbus banks. in addition, the qbc handles internal memory contentions. qbc sc140 core data alu because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 pin assignments freescale semiconductor 4 1 pin assignments this section includes diagrams of the msc8113 package ball grid array layouts and pinout allocation tables. 1.1 fc-pbga ball layout diagrams top and bottom views of the fc-pbga package are shown in figure 3 and figure 4 with their ball location index numbers. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
pin assignments msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 5 figure 3. msc8113 package, top view 2345678910111213141516171819202122 b v dd gnd gnd nmi_ out gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gpio0 v dd v dd gnd cgnd v dd tdo s reset gpio28 hcid1 gnd v dd gnd v dd gnd v dd gnd gnd gpio30 gpio2 gpio1 gpio7 gpio3 gpio5 gpio6 d tdi ee0 ee1 gnd v ddh hcid2 hcid3 gnd v dd gnd v dd gnd v dd v dd gpio31 gpio29 v ddh gpio4 v ddh gnd gpio8 e tck trst tms hreset gpio27 hcid0 gnd v dd gnd v dd gnd v dd gnd gnd v dd gnd gnd gpio9 gpio13 gpio10 gpio1 2 f po reset rst conf nmi ha29 ha22 gnd v dd v dd v dd gnd v dd gnd v dd ethrx_ clk ethtx_ clk gpio20 gpio18 gpio16 gpio11 gpio14 gpio1 9 gha24ha27ha25ha23ha17pwe0 v dd v dd baddr 31 bm0 abb v dd int_ out ethcr s v dd cs1 bctl0 gpio15 gnd gpio17 gpio2 2 hha20 ha28 v dd ha19 test psd cas pgta v dd bm1 artry aack dbb hta v dd tt4 cs4 gpio24 gpio21 v dd v ddh a31 jha18ha26 v dd ha13 gnd psda mux baddr 27 v dd clkin bm2 dbg v dd gnd v dd tt3 psda10 bctl1 gpio23 gnd gpio25 a30 k ha15 ha21 ha16 pwe3 pwe1 poe baddr 30 res. gnd gnd gnd gnd clkout v dd tt2 ale cs2 gnd a26 a29 a28 lha12ha14ha11 v ddh v ddh baddr 28 baddr 29 gnd gnd gnd v ddh gnd gnd cs3 v ddh a27 a25 a22 m hd28 hd31 v ddh gnd gnd gnd v dd v ddh gnd gnd v ddh hb rst v ddh v ddh gnd v ddh a24 a21 n hd26 hd30 hd29 hd24 pwe2 v ddh hwbs 0 hbcs gnd gnd hrds bg hcs cs0 psdwe gpio26 a23 a20 p hd20 hd27 hd25 hd23 hwbs 3 hwbs 2 hwbs 1 hclkin gnd gnd syn v ccsyn gnd gnd ta br tea psd val dp0 v ddh gnd a19 r hd18 v ddh gnd hd22 hwbs 6 hwbs 4 tsz1 tsz3 gbl v dd v dd v dd tt0 dp7 dp6 dp3 ts dp2 a17 a18 a16 t hd17 hd21 hd1 hd0 hwbs 7 hwbs 5 tsz0 tsz2 tbst v dd d16 tt1 d21 d23 dp5 dp4 dp1 d30 gnd a15 a14 u hd16 hd19 hd2 d2 d3 d6 d8 d9 d11 d14 d15 d17 d19 d22 d25 d26 d28 d31 v ddh a12 a13 v hd3 v ddh gndd0d1d4d5d7d10d12d13d18d20gndd24d27d29a8a9a10a11 w hd6 hd5 hd4 gnd gnd v ddh v ddh gnd hdst1 hdst0 v ddh gnd hd40 v ddh hd33 v ddh hd32 gnd gnd a7 a6 y hd7 hd15 v ddh hd9 v dd hd60 hd58 gnd v ddh hd51 gnd v ddh hd43 gnd v ddh gnd hd37 hd34 v ddh a4 a5 aa v dd hd14 hd12 hd10 hd63 hd59 gnd v ddh hd54 hd52 v ddh gnd v ddh hd46 gnd hd42 hd38 hd35 a0 a2 a3 ab gnd hd13 hd11 hd8 hd62 hd61 hd57 hd56 hd55 hd53 hd50 hd49 hd48 hd47 hd45 hd44 hd41 hd39 hd36 a1 v dd top view msc8113 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 pin assignments freescale semiconductor 6 figure 4. msc8113 package, bottom view 2221201918171615141312111098765432 bgnd v dd v dd gpio0 v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd v dd gnd nmi_ out gnd gnd v dd c gpio6 gpio5 gpio3 gpio7 gpio1 gpio2 gpio30 gnd gnd v dd gnd v dd gnd v dd gnd hcid1 gpio28 s reset tdo v dd gnd d gpio8 gnd v ddh gpio4 v ddh gpio29 gpio31 v dd v dd gnd v dd gnd v dd gnd hcid3 hcid2 v ddh gnd ee1 ee0 tdi e gpio12 gpio10 gpio13 gpio9 gnd gnd v dd gnd gnd v dd gnd v dd gnd v dd gnd hcid0 gpio27 hreset tms trst tck f gpio19 gpio14 gpio11 gpio16 gpio18 gpio20 ethtx_ clk ethrx_ clk v dd gnd v dd gnd v dd v dd v dd gnd ha22 ha29 nmi rst conf po reset g gpio22 gpio17 gnd gpio15 bctl0 cs1 v dd ethcr s int_ out v dd abb bm0 baddr 31 v dd v dd pwe0 ha17 ha23 ha25 ha27 ha24 ha31 v ddh v dd gpio21 gpio24 cs4 tt4 v dd hta dbb aack artry bm1 v dd pgta psd cas test ha19 v dd ha28 ha20 j a30 gpio25 gnd gpio23 bctl1 psda10 tt3 v dd gnd v dd dbg bm2 clkin v dd baddr 27 psda mux gnd ha13 v dd ha26 ha18 ka28 a29 a26 gnd cs2 ale tt2 v dd clkout gnd gnd gnd gnd res. baddr 30 poe pwe1 pwe3 ha16 ha21 ha15 la22 a25 a27 v ddh cs3 gnd gnd v ddh gnd gnd gnd baddr 29 baddr 28 v ddh v ddh ha11 ha14 ha12 ma21 a24 v ddh gnd v ddh v ddh hb rst v ddh gnd gnd v ddh v dd gnd gnd gnd v ddh hd31 hd28 n a20 a23 gpio26 psdwe cs0 hcs bg hrds gnd gnd hbcs hwbs 0 v ddh pwe2 hd24 hd29 hd30 hd26 pa19 gnd v ddh dp0 psd va l tea br ta gnd gnd v ccsyn gnd syn gnd hclkin hwbs 1 hwbs 2 hwbs 3 hd23 hd25 hd27 hd20 ra16 a18 a17 dp2 ts dp3 dp6 dp7 tt0 v dd v dd v dd gbl tsz3 tsz1 hwbs 4 hwbs 6 hd22 gnd v ddh hd18 t a14 a15 gnd d30 dp1 dp4 dp5 d23 d21 tt1 d16 v dd tbst tsz2 tsz0 hwbs 5 hwbs 7 hd0 hd1 hd21 hd17 ua13 a12 v ddh d31 d28 d26 d25 d22 d19 d17 d15 d14 d11 d9 d8 d6 d3 d2 hd2 hd19 hd16 v a11 a10 a9 a8 d29 d27 d24 gnd d20 d18 d13 d12 d10 d7 d5 d4 d1 d0 gnd v ddh hd3 wa6 a7 gndgndhd32 v ddh hd33 v ddh hd40 gnd v ddh hdst0 hdst1 gnd v ddh v ddh gnd gnd hd4 hd5 hd6 ya5 a4 v ddh hd34 hd37 gnd v ddh gnd hd43 v ddh gnd hd51 v ddh gnd hd58 hd60 v dd hd9 v ddh hd15 hd7 aa a3 a2 a0 hd35 hd38 hd42 gnd hd46 v ddh gnd v ddh hd52 hd54 v ddh gnd hd59 hd63 hd10 hd12 hd14 v dd ab v dd a1 hd36 hd39 hd41 hd44 hd45 hd47 hd48 hd49 hd50 hd53 hd55 hd56 hd57 hd61 hd62 hd8 hd11 hd13 gnd bottom view msc 8 113 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
pin assignments msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 7 1.2 signal list by ball location table 1 presents signal list sorted by ball number. - table 1. msc8113 signal listing by ball designator des. signal name des. signal name b3 v dd c18 gpio1/timer0/chip_id1/irq5 /ethtxd1 b4 gnd c19 gpio7/tdm3rclk/irq5 /ethtxd3 b5 gnd c20 gpio3/tdm3tsyn/irq1 /ethtxd2 b6 nmi_out c21 gpio5/tdm3tdat/irq3 /ethrxd3 b7 gnd c22 gpio6/tdm3rsyn/irq4 /ethrxd2 b8 v dd d2 tdi b9 gnd d3 ee0 b10 v dd d4 ee1 b11 gnd d5 gnd b12 v dd d6 v ddh b13 gnd d7 hcid2 b14 v dd d8 hcid3/ha8 b15 gnd d9 gnd b16 v dd d10 v dd b17 gnd d11 gnd b18 v dd d12 v dd b19 gpio0/chip_id0/irq4 /ethtxd0 d13 gnd b20 v dd d14 v dd b21 v dd d15 v dd b22 gnd d16 gpio31/timer3/scl c2 gnd d17 gpio29/chip_id3/ethtx_en c3 v dd d18 v ddh c4 tdo d19 gpio4/tdm3tclk/irq2 /ethtx_er c5 sreset d20 v ddh c6 gpio28/utxd/dreq2 d21 gnd c7 hcid1 d22 gpio8/tdm3rdat/irq6 /ethcol c8 gnd e2 tck c9 v dd e3 trst c10 gnd e4 tms c11 v dd e5 hreset c12 gnd e6 gpio27/urxd/dreq1 c13 v dd e7 hcid0 c14 gnd e8 gnd c15 gnd e9 v dd c16 gpio30/timer2/tmclk/sda e10 gnd c17 gpio2/timer1/chip_id2/irq6 e11 v dd because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 pin assignments freescale semiconductor 8 e12 gnd g6 ha17 e13 v dd g7 pwe0 /psddqm0 /pbs0 e14 gnd g8 v dd e15 gnd g9 v dd e16 v dd g10 irq3 /baddr31 e17 gnd g11 bm0/tc0/bnksel0 e18 gnd g12 abb /irq4 e19 gpio9/tdm2tsyn/irq7 /ethmdio g13 v dd e20 gpio13/tdm2rclk/irq11 /ethmdc g14 irq7 /int_out e21 gpio10/tdm2tclk/irq8 /ethrx_dv/ethcrs_dv/nc g15 ethcrs/ethrxd e22 gpio12/tdm2rsyn/irq10 /ethrxd1/ethsync g16 v dd f2 poreset g17 cs1 f3 rstconf g18 bctl0 f4 nmi g19 gpio15/tdm1tsyn/dreq1 f5 ha29 g20 gnd f6 ha22 g21 gpio17/tdm1tdat/dack1 f7 gnd g22 gpio22/tdm0tclk/done2 /drack2 f8 v dd h2 ha20 f9 v dd h3 ha28 f10 v dd h4 v dd f11 gnd h5 ha19 f12 v dd h6 test f13 gnd h7 psdcas /pgpl3 f14 v dd h8 pgta /pupmwait/pgpl4/ppbs f15 ethrx_clk/ethsync_in h9 v dd f16 ethtx_clk/ethref_clk/ethclock h10 bm1/tc1/bnksel1 f17 gpio20/tdm1rdat h11 artry f18 gpio18/tdm1rsyn/dreq2 h12 aack f19 gpio16/tdm1tclk/done1 /drack1 h13 dbb /irq5 f20 gpio11/tdm2tdat/irq9 /ethrx_er/ethtxd h14 hta f21 gpio14/tdm2rdat/irq12 /ethrxd0/nc h15 v dd f22 gpio19/tdm1rclk/dack2 h16 tt4/cs7 g2 ha24 h17 cs4 g3 ha27 h18 gpio24/tdm0rsyn/irq14 g4 ha25 h19 gpio21/tdm0tsyn g5 ha23 h20 v dd table 1. msc8113 signal listing by ball designator (continued) des. signal name des. signal name because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
pin assignments msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 9 h21 v ddh k15 v dd h22 a31 k16 tt2/cs5 j2 ha18 k17 ale j3 ha26 k18 cs2 j4 v dd k19 gnd j5 ha13 k20 a26 j6 gnd k21 a29 j7 psdamux/pgpl5 k22 a28 j8 baddr27 l2 ha12 j9 v dd l3 ha14 j10 clkin l4 ha11 j11 bm2/tc2/bnksel2 l5 v ddh j12 dbg l6 v ddh j13 v dd l7 baddr28 j14 gnd l8 irq5 /baddr29 j15 v dd l9 gnd j16 tt3/cs6 l10 gnd j17 psda10/pgpl0 l14 gnd j18 bctl1 /cs5 l15 v ddh j19 gpio23/tdm0tdat/irq13 l16 gnd j20 gnd l17 gnd j21 gpio25/tdm0rclk/irq15 l18 cs3 j22 a30 l19 v ddh k2 ha15 l20 a27 k3 ha21 l21 a25 k4 ha16 l22 a22 k5 pwe3 /psddqm3 /pbs3 m2 hd28 k6 pwe1 /psddqm1 /pbs1 m3 hd31 k7 poe /psdras /pgpl2 m4 v ddh k8 irq2 /baddr30 m5 gnd k9 reserved m6 gnd k10 gnd m7 gnd k11 gnd m8 v dd k12 gnd m9 v ddh k13 gnd m10 gnd k14 clkout m14 gnd table 1. msc8113 signal listing by ball designator (continued) des. signal name des. signal name because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 pin assignments freescale semiconductor 10 m15 v ddh p12 v ccsyn m16 hbrst p13 gnd m17 v ddh p14 gnd m18 v ddh p15 ta m19 gnd p16 br m20 v ddh p17 tea m21 a24 p18 psdval m22 a21 p19 dp0/dreq1/ext_br2 n2 hd26 p20 v ddh n3 hd30 p21 gnd n4 hd29 p22 a19 n5 hd24 r2 hd18 n6 pwe2 /psddqm2 /pbs2 r3 v ddh n7 v ddh r4 gnd n8 hwbs0 /hdbs0 /hwbe0 /hdbe0 r5 hd22 n9 hbcs r6 hwbs6 /hdbs6 /hwbe6 /hdbe6 /pwe6 /psddqm6 /pbs6 n10 gnd r7 hwbs4 /hdbs4 /hwbe4 /hdbe4 /pwe4 /psddqm4 /pbs4 n14 gnd r8 tsz1 n15 hrds /hrw/hrde r9 tsz3 n16 bg r10 irq1 /gbl n17 hcs r11 v dd n18 cs0 r12 v dd n19 psdwe /pgpl1 r13 v dd n20 gpio26/tdm0rdat r14 tt0/ha7 n21 a23 r15 irq7 /dp7/dreq4 n22 a20 r16 irq6 /dp6/dreq3 p2 hd20 r17 irq3 /dp3/dreq2/ext_br3 p3 hd27 r18 ts p4 hd25 r19 irq2 /dp2/dack2 /ext_dbg2 p5 hd23 r20 a17 p6 hwbs3 /hdbs3 /hwbe3 /hdbe3 r21 a18 p7 hwbs2 /hdbs2 /hwbe2 /hdbe2 r22 a16 p8 hwbs1 /hdbs1 /hwbe1 /hdbe1 t2 hd17 p9 hclkin t3 hd21 p10 gnd t4 hd1/dsisync p11 gnd syn t5 hd0/swte table 1. msc8113 signal listing by ball designator (continued) des. signal name des. signal name because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
pin assignments msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 11 t6 hwbs7 /hdbs7 /hwbe7 /hdbe7 /pwe7 /psddqm7 /pbs7 u21 a12 t7 hwbs5 /hdbs5 /hwbe5 /hdbe5 /pwe5 /psddqm5 /pbs5 u22 a13 t8 tsz0 v2 hd3/modck1 t9 tsz2 v3 v ddh t10 tbst v4 gnd t11 v dd v5 d0 t12 d16 v6 d1 t13 tt1 v7 d4 t14 d21 v8 d5 t15 d23 v9 d7 t16 irq5 /dp5/dack4 /ext_bg3 v10 d10 t17 irq4 /dp4/dack3 /ext_dbg3 v11 d12 t18 irq1 /dp1/dack1 /ext_bg2 v12 d13 t19 d30 v13 d18 t20 gnd v14 d20 t21 a15 v15 gnd t22 a14 v16 d24 u2 hd16 v17 d27 u3 hd19 v18 d29 u4 hd2/dsi64 v19 a8 u5 d2 v20 a9 u6 d3 v21 a10 u7 d6 v22 a11 u8 d8 w2 hd6 u9 d9 w3 hd5/cnfgs u10 d11 w4 hd4/modck2 u11 d14 w5 gnd u12 d15 w6 gnd u13 d17 w7 v ddh u14 d19 w8 v ddh u15 d22 w9 gnd u16 d25 w10 hdst1/ha10 u17 d26 w11 hdst0/ha9 u18 d28 w12 v ddh u19 d31 w13 gnd u20 v ddh w14 hd40/d40/ethrxd0 table 1. msc8113 signal listing by ball designator (continued) des. signal name des. signal name because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 pin assignments freescale semiconductor 12 w15 v ddh aa9 v ddh w16 hd33/d33/reserved aa10 hd54/d54/ethtx_en w17 v ddh aa11 hd52/d52 w18 hd32/d32/reserved aa12 v ddh w19 gnd aa13 gnd w20 gnd aa14 v ddh w21 a7 aa15 hd46/d46/ethtxt0 w22 a6 aa16 gnd y2 hd7 aa17 hd42/d42/ethrxd2/reserved y3 hd15 aa18 hd38/d38/reserved y4 v ddh aa19 hd35/d35/reserved y5 hd9 aa20 a0 y6 v dd aa21 a2 y7 hd60/d60/ethcol/reserved aa22 a3 y8 hd58/d58/ethmdc ab2 gnd y9 gnd ab3 hd13 y10 v ddh ab4 hd11 y11 hd51/d51 ab5 hd8 y12 gnd ab6 hd62/d62 y13 v ddh ab7 hd61/d61 y14 hd43/d43/ethrxd3/reserved ab8 hd57/d57/ethrx_er y15 gnd ab9 hd56/d56/ethrx_dv/ethcrs_dv y16 v ddh ab10 hd55/d55/ethtx_er/reserved y17 gnd ab11 hd53/d53 y18 hd37/d37/reserved ab12 hd50/d50 y19 hd34/d34/reserved ab13 hd49/d49/ethtxd3/reserved y20 v ddh ab14 hd48/d48/ethtxd2/reserved y21 a4 ab15 hd47/d47/ethtxd1 y22 a5 ab16 hd45/d45 aa2 v dd ab17 hd44/d44 aa3 hd14 ab18 hd41/d41/ethrxd1 aa4 hd12 ab19 hd39/d39/reserved aa5 hd10 ab20 hd36/d36/reserved aa6 hd63/d63 ab21 a1 aa7 hd59/d59/ethmdio ab22 v dd aa8 gnd table 1. msc8113 signal listing by ball designator (continued) des. signal name des. signal name because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 13 2 electrical characteristics this document contains detailed information on power co nsiderations, dc/ac electrical characteristics, and ac timing specifications. for addition al information, see the msc8113 reference manual . 2.1 maximum ratings in calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. a maximum specification is cal culated using a worst case variation of process parameter values in one direction. the minimum specification is calculated using the worst case for the same parameters in the opposite directio n. therefore, a ?maximum? value for a specification never occurs in the same device with a ?minimum? value for another specification; adding a maximum to a minimum represents a condition that can never exist. table 2 describes the maximum electri cal ratings for the msc8113. caution this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either gnd or v dd ). table 2. absolute maximum ratings rating symbol value unit core and pll supply voltage v dd ?0.2 to 1.6 v i/o supply voltage v ddh ?0.2 to 4.0 v input voltage v in ?0.2 to 4.0 v maximum operating temperature: t j 105 c minimum operating temperature t j ?40 c storage temperature range t stg ?55 to +150 c notes: 1. functional operating conditions are given in table 3. 2. absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond the listed limits may affect device reliability or cause permanent damage. 3. section 3.5 , thermal considerations includes a formula for computing the chip junction temperature (t j ). because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 14 2.2 recommended operating conditions table 3 lists recommended operating conditions. proper device op eration outside of these conditions is not guaranteed. 2.3 thermal characteristics table 4 describes thermal characteristics of the msc8113 for the fc-pbga packages. section 3.5 , thermal considerations provides a detailed explanation of these characteristics. 2.4 dc electrical characteristics this section describes the dc electrical characteristics for the msc8113. the measurements in table 5 assume the following system conditions: ?t a = 25 c ? v dd = 1.1 v nominal = 1.07?1.13 v dc ? v ddh = 3.3 v 5% v dc ? gnd = 0 v dc note: the leakage current is measured for nominal v ddh and v dd . table 3. recommended operating conditions rating symbol value unit core and pll supply voltage: v dd v ccsyn 1.07 to 1.13 v i/o supply voltage v ddh 3.135 to 3.465 v input voltage v in ?0.2 to v ddh +0.2 v operating temperature range: t j ?40 to 105 c table 4. thermal characteristics for the msc8113 characteristic symbol fc-pbga 20 20 mm 5 unit natural convection 200 ft/min (1 m/s) airflow junction-to-ambient 1, 2 r ja 26 21 c/w junction-to-ambient, four-layer board 1, 3 r ja 19 15 c/w junction-to-board (bottom) 4 r jb 9 c/w junction-to-case 5 r jc 0.9 c/w junction-to-package-top 6 jt 1 c/w notes: 1. junction temperature is a func tion of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 wit h the board horizontal. 4. thermal resistance between the die and the printed circuit boar d per jedec jesd 51-8. boar d temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per jedec jesd51-2. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 15 table 5. dc electrical characteristics characteristic symbol min typical max unit input high voltage 1 , all inputs except clkin v ih 2.0 ? 3.465 v input low voltage 1 v il gnd 0 0.8 v clkin input high voltage v ihc 2.4 3.0 3.465 v clkin input low voltage v ilc gnd 0 0.8 v input leakage current, v in = v ddh i in ?1.0 0.09 1 a tri-state (high impedance off state) leakage current, v in = v ddh i oz ?1.0 0.09 1 a signal low input current, v il = 0.8 v 2 i l ?1.0 0.09 1 a signal high input current, v ih = 2.0 v 2 i h ?1.0 0.09 1 a output high voltage, i oh = ?2 ma, except open drain pins v oh 2.0 3.0 ? v output low voltage, i ol = 3.2 ma v ol ?00 . 4v internal supply current: ? wait mode ? stop mode i ddw i dds ? ? 375 3 290 3 ? ? ma ma typical power 400 mhz at 1.1 v 4 typical power 300 mhz at 1.1 v 4 p? ? 826 676 ? ? mw mw notes: 1. see figure 5 for undershoot and overshoot voltages. 2. not tested. guaranteed by design. 3. measured for 1.1 v core at 25c junction temperature. 4. the typical power values were calculated using a power calcul ator configured for three cores performing an efr code with the device running at the specified operating frequency and a junction temperature of 25c. no peripherals were included. the calculator was created using codewarrior ? 2.5. these values are provided as ex amples only. power consumption is application dependent and varies widely. to assure proper board des ign with regard to thermal dissipation and maintaining proper operating temperatures, evaluate power consumption for your applic ation and use the design guidelines in section 3 of this document and in msc8102, msc8122, and msc8126 thermal management design guidelines (an2601). figure 5. overshoot/undershoot voltage for v ih and v il gnd gnd ? 0.3 v gnd ? 0.7 v v il v ih must not exceed 10% of clock period v ddh + 17% v ddh + 8% v ddh because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 16 2.5 ac timings the following sections include illustrations and tables of cloc k diagrams, signals, and parallel i/o outputs and inputs. when systems such as dsp farms are developed using the dsi, use a device loading of 4 pf per pin. ac timings are based on a 20 pf load, except where noted otherwise, and a 50 transmission line. for loads smaller than 20 pf, subtract 0.06 ns per pf down to 10 pf load. for loads larger than 20 pf, add 0.06 ns for siu/ethernet/dsi delay and 0.07 ns for gpio/tdm/timer delay. when calculating overall loading, also consider additional rc delay. 2.5.1 output buffer impedances 2.5.2 start-up timing starting the device requires coordination among several input sequences including clocking, reset, and power. section 2.5.3 describes the clocking characteristics. section 2.5.4 describes the reset and power-up characteristics. you must use the following guidelines when starting up an msc8113 device: ? poreset and trst must be asserted externally for the duration of the power-up sequence. see table 11 for timing. ? if possible, bring up the v dd and v ddh levels together. for designs with separate power supplies, bring up the v dd levels and then the v ddh levels (see figure 7 ). ? clkin should start toggling at least 16 cycles (starting after v ddh reaches its nominal level) before poreset deassertion to guarantee correct device operation (see figure 6 and figure 7 ). ? clkin must not be pulled high during v ddh power-up. clkin can toggle during this period. the following figures show acceptable start-up sequence examples. figure 6 shows a sequence in which v dd and v ddh are raised together. figure 7 shows a sequence in which v ddh is raised after v dd and clkin begins to toggle as v ddh rises. table 6. output buffer impedances output buffers typical impedance ( ) system bus 50 memory controller 50 parallel i/o 50 note: these are typical values at 65c. the impedance may vary by 25% depending on device proc ess and operating temperature. figure 6. start-up sequence: v dd and v ddh raised together voltage time o.5 v 3.3 v 1.1 v v ddh nominal level poreset /trst asserted v dd nominal level clkin starts toggling v dd /v ddh applied poreset /trst deasserted 1 2.2 v v ddh = nominal value v dd = nominal value because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 17 in all cases, the power-up sequence must follow the guidelines shown in figure 8 . the following rules apply: 1. during time interval a, v ddh should always be equal to or less than the v dd / v ccsyn voltage level. the duration of interval a should be kept below 10 ms. 2. the duration of timing interval b should be kept as small as possible and less than 10 ms. 2.5.3 clock and timing signals the following sections include a description of clock signal characteristics. ta bl e 7 shows the maximum frequency values for internal (core, reference, bus, and dsi) and external ( clkin and clkout ) clocks. the user must ensure that maximum frequency values are not exceeded. figure 7. start-up sequence: v dd raised before v ddh with clkin started with v ddh figure 8. power-up sequence for v ddh and v dd /v ccsyn table 7. maximum frequencies characteristic maximum in mhz core frequency 300/400 reference frequency (refclk) 100/133 voltage time o.5 v 3.3 v 1.1 v v ddh nominal poreset /trst asserted v dd nominal clkin starts toggling v dd applied poreset /trst deasserted 1 v ddh applied v ddh = nominal v dd = nominal 3.3 v 1.2 v a b v dd /v ccsyn v ddh (io) t (time ) v because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 18 2.5.4 reset timing the msc8113 has several inputs to the reset logic: ? power-on reset ( poreset ) ? external hard reset ( hreset ) ? external soft reset ( sreset ) ? software watchdog reset ? bus monitor reset ? host reset command through jtag all msc8113 reset sources are fed into the reset controller, whic h takes different actions depending on the source of the reset . the reset status register indicates the most recent sources to cause a reset. table 10 describes the reset sources. internal bus frequency (blck) 100/133 dsi clock frequency (hclkin) ? core frequency = 300 mhz ? core frequency = 400 mhz hclkin (min{70 mhz, clkout}) hclkin (min{100 mhz, clkout}) external clock frequency (clkin or clkout) 100/133 table 8. clock frequencies characteristics symbol 300 mhz device 400 mhz device minmaxminmax clkin frequency f clkin 20 100 20 133.3 bclk frequency f bclk 40 100 40 133.3 reference clock (refclk) frequency f refclk 40 100 40 133.3 output clock (clkout) frequency f clkout 40 100 40 133.3 sc140 core clock frequency f core 200 300 200 400 note: the rise and fall time of external clocks should be 3 ns maximum table 9. system clock parameters characteristic min max unit phase jitter between bclk and clkin ? 0.3 ns clkin frequency 20 see table 8 mhz clkin slope ?3n s pll input clock (after predivider) 20 100 mhz pll output frequency (vco output) ? 300 mhz core ? 400 mhz core 800 1200 1600 mhz mhz mhz clkout frequency jitter 1 ? 200 ps clkout phase jitter 1 with clkin phase jitter of 100 ps. ? 500 ps notes: 1. peak-to-peak. 2. not tested. guaranteed by design. table 7. maximum frequencies characteristic maximum in mhz because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 19 table 11 summarizes the reset actions that occur as a result of the different reset sources. 2.5.4.1 power-on reset (poreset ) pin asserting poreset initiates the power-on reset flow. poreset must be asserted externally for at least 16 clkin cycles after v dd and v ddh are both at their nominal levels. table 10. reset sources name direction description power-on reset (poreset ) input initiates the power-on reset flow that resets the msc8113 and configures various attributes of the msc8113. on poreset , the entire msc8113 device is reset. spll states is reset, hreset and sreset are driven, the sc140 extended cores are reset, and system configuration is sampled. the clock mode (modck bits), reset configuration mode, boot mode, chip id, and use of either a dsi 64 bits port or a system bus 64 bits port are configured only when poreset is asserted. external hard reset (hreset ) input/ output initiates the hard reset flow that configures various attributes of the msc8113. while hreset is asserted, sreset is also asserted. hreset is an open-drain pin. upon hard reset, hreset and sreset are driven, the sc140 extended cores are reset, and system configuration is sampled. the most configurable features are reconfigured. these features are defined in the 32-bit hard reset configuration word described in hard reset configuration word section of the reset chapter in the msc8113 reference manual . external soft reset (sreset ) input/ output initiates the soft reset flow. the msc8113 detects an external assertion of sreset only if it occurs while the msc8113 is not asserting reset. sreset is an open-drain pin. upon soft reset, sreset is driven, the sc140 extended cores are reset, and system configuration is maintained. software watchdog reset internal when the msc8113 watchdog count reaches zero , a software watchdog reset is signalled. the enabled software watchdog event then generates an internal hard reset sequence. bus monitor reset internal when the msc8113 bus monitor count reaches zero, a bus monitor hard reset is asserted. the enabled bus monitor event then generates an internal hard reset sequence. host reset command through the tap internal when a host reset command is written through the test access port (tap), the tap logic asserts the soft reset signal and an internal soft reset sequence is generated. table 11. reset actions for each reset source reset action/reset source power-on reset (poreset ) hard reset (hreset ) soft reset (sreset ) external only external or internal (software watchdog or bus monitor) external jtag command: extest, clamp, or highz configuration pins sampled (refer to section 2.5.4.1 for details) . yes nonono spll state reset yes no no no system reset configuration write through the dsi y e s n on on o system reset configuration write though the system bus yes yes no no hreset driven yes yes no no siu registers reset yes yes no no ipbus modules reset (tdm, uart, timers, dsi, ipbus master, gic, hs, and gpio) yes yes yes yes sreset driven yes yes yes depends on command sc140 extended cores reset yes yes yes yes mqbs reset yes yes yes yes because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 20 2.5.4.2 reset configuration the msc8113 has two mechanisms for writing the reset configuration: ? through the direct slave interface (dsi) ? through the system bus. when the reset configuration is written through the system bus, the msc8113 acts as a configuration master or a configuration slave. if configura tion slave is selected, but no special configuration word is written, a default configuration word is applied. fourteen signal levels (see chapter 1 for signal description details) are sampled on poreset deassertion to define the reset configuration mode and boot and operating conditions: ? rstconf ? cnfgs ? dsisync ? dsi64 ? chip_id[0?3] ? bm[0?2] ? swte ? modck[1?2] 2.5.4.3 reset timing tables table 12 and figure 9 describe the reset timing for a reset configurati on write through the direct slave interface (dsi) or through the system bus. table 12. timing for a reset configuration write through the dsi or system bus no. characteristics expression min max unit 1 required external poreset duration minimum ? clkin = 20 mhz ? clkin = 100 mhz (300 mhz core) ? clkin = 133 mhz (400 mhz core) 16/clkin 800 160 120 ? ? ? ns ns ns 2 delay from deassertion of external poreset to deassertion of internal poreset ? clkin = 20 mhz to 133 mhz 1024/clkin 6.17 51.2 s 3 delay from de-assertion of internal poreset to spll lock ? clkin = 20 mhz (rdf = 1) ? clkin = 100 mhz (rdf = 1) (300 mhz core) ? clkin = 133 mhz (rdf = 2) (400 mhz core) 6400/(clkin/rdf) (pll reference clock-division factor) 320 64 96 320 64 96 s s s 5 delay from spll to hreset deassertion ? refclk = 40 mhz to 133 mhz 512/refclk 3.08 12.8 s 6 delay from spll lock to sreset deassertion ? refclk = 40 mhz to 133 mhz 515/refclk 3.10 12.88 s 7 setup time from assertion of rstconf , cnfgs, dsisync, dsi64, chip_id[0?3], bm[0?2], swte, and modck[1?2] before deassertion of poreset 3?ns 8 hold time from deassertion of poreset to deassertion of rstconf , cnfgs, dsisync, dsi64, chip_id[0?3], bm[0?2], swte, and modck[1?2] 5?ns note: timings are not tested, but are guaranteed by design. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 21 2.5.5 system bus access timing 2.5.5.1 core data transfers generally, all msc8113 bus and system output signals are driven from the rising edge of the reference clock (refclk). the refclk is the clkin signal. memory controller signals, however, trigger on four points within a refclk cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge of refclk (and t3 at the falling edge), but the spacing of t2 and t4 depe nds on the pll clock ratio selected, as table 13 shows. figure 10 is a graphical representation of table 13 . figure 9. timing diagram for a reset configuration write table 13. tick spacing for memory controller signals bclk/sc140 clock tick spacing (t1 occurs at the rising edge of refclk) t2 t3 t4 1:4, 1:6, 1:8, 1:10 1/4 refclk 1/2 refclk 3/4 refclk 1:3 1/6 refclk 1/2 refclk 4/6 refclk 1:5 2/10 refclk 1/2 refclk 7/10 refclk figure 10. internal tick spacing for memory controller signals poreset internal hreset input output (i/o) sreset output (i/o) rstconf , cnfgs, dsisync, dsi64 chip_id[0?3], bm[0?2], swte, modck[1?2] host programs word spll is locked (no external indication) poreset reset configuration pins are sampled 1 2 modck[3?5] 1 + 2 3 5 6 spll locking period reset configuration write sequence during this period. refclk t1 t2 t3 t4 refclk t1 t2 t3 t4 for 1:3 for 1:5 refclk t1 t2 t3 t4 for 1:4, 1:6, 1:8, 1:10 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 22 the upm machine and gpcm machine outputs change on the internal tick selected by the memory controller configuration. the ac timing specifications are relative to the inte rnal tick. sdram machine outputs change only on the refclk rising edge. table 14. ac timing for siu inputs no. characteristic ref = clkin at 1.1 v and 100/133 mhz units 10 hold time for all signals after the 50% level of the refclk rising edge 0.5 ns 11a artry /abb set-up time before the 50% level of the refclk rising edge 3.1 ns 11b dbg /dbb /bg /br /tc set-up time before the 50% level of the refclk rising edge 3.6 ns 11c aack set-up time before the 50% level of the refclk rising edge 3.0 ns 11d ta /tea /psdval set-up time before the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 3.5 4.4 ns ns 12 data bus set-up time before refclk rising edge in normal mode ? data-pipeline mode ? non-pipeline mode 1.9 4.2 ns ns 13 1 data bus set-up time before the 50% level of the refclk rising edge in ecc and parity modes ? data-pipeline mode ? non-pipeline mode 2.0 8.2 ns ns 14 1 dp set-up time before the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 2.0 7.9 ns ns 15a ts and address bus set-up time before the 50% level of the refclk rising edge ? extra cycle mode (siubcr[exdd] = 0) ? no extra cycle mode (siubcr[exdd] = 1) 4.2 5.5 ns ns 15b address attributes: tt/tbst /tsz/gbl set-up time before the 50% level of the refclk rising edge ? extra cycle mode (siubcr[exdd] = 0) ? no extra cycle mode (siubcr[exdd] = 1) 3.7 4.8 ns ns 16 pupmwait signal set-up time before the 50% level of the refclk rising edge 3.7 ns 17 irqx setup time before the 50% level; of the refclk rising edge 3 4.0 ns 18 irqx minimum pulse width 3 6.0 + t refclk ns notes: 1. timings specifications 13 and 14 in non-pipeline mode are more restrictive than msc8102 timings. 2. values are measured from the 50% ttl transition level relative to the 50% level of the refclk rising edge. 3. guaranteed by design. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 23 table 15. ac timing for siu outputs no. characteristic bus speed in mhz 3 ref = clkin at 1.1 v and 100/ 133 mhz units 30 2 minimum delay from the 50% level of the refclk for all signals 0.9 ns 31 psdval /tea /ta max delay from the 50% level of the refclk rising edge 6.0 ns 32a address bus max delay from the 50% level of the refclk rising edge ? multi-master mode (siubcr[ebm] = 1) ? single-master mode (siubcr[ebm] = 0) 6.4 5.3 ns ns 32b address attributes: tt[0?1]/tbst /tsz/gbl max delay from the 50% level of the refclk rising edge 6.4 ns 32c address attributes: tt[2?4]/tc max delay from the 50% level of the refclk rising edge 6.9 ns 32d baddr max delay from the 50% level of the refclk rising edge 5.2 ns 33a data bus max delay from the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 4.8 7.1 ns ns 33b dp max delay from the 50% level of the refclk rising edge ? data-pipeline mode ? non-pipeline mode 6.0 7.5 ns ns 34 memory controller signals/ale/cs[0?4] max delay from the 50% level of the refclk rising edge 5.1 ns 35a dbg /bg /br /dbb max delay from the 50% level of the refclk rising edge 6.0 ns 35b aack /abb /ts /cs[5?7] max delay from the 50% level of the refclk rising edge 5.5 ns notes: 1. values are measured from the 50% level of the refclk risi ng edge to the 50% signal level and assume a 20 pf load except where otherwise specified. 2. except for specification 30, which is specified for a 10 pf l oad, all timings in this table are specified for a 20 pf load. decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pf decrease in load. increasing the load results i n a timing increase at the rate of 0.15 ns per 5 pf increase in load. 3. the maximum bus frequency depends on the mode: ? in 60x-compatible mode connected to another msc8113 device, the frequency is determined by adding the input and output longest timing values, which results in the total delay for 20 pf output capacitance. you must also account for other influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on. ? in single-master mode, the frequency depends on t he timing of the devices connected to the msc8113. ? to achieve maximum performance on the bus in single-master mode, disable the dbb signal by writing a 1 to the siumcr[bdd] bit. see the siu chapter in the msc8113 reference manual for details. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 24 figure 11. siu timing diagram refclk aack /artry /ta /tea /dbg /bg /br data bus inputs?normal mode pupmwait input psdva l/tea /ta outputs address bus/tt[0?4]/tc[0?2]/tbst /tsz[0?3]/gbl outputs data bus outputs min delay for all output pins 11 10 10 10 12 15 31 32a/b 33a 30 dp outputs 33b memory controller/ale outputs 34 data bus inputs?ecc and parity modes 10 13 aack /abb /ts /dbg /bg /br /dbb /cs outputs 35 baddr outputs 32c dp inputs 14 address bus/ts /tt[0?4]/tc[0?2]/ 16 psdval /abb /dbb inputs tbst /tsz[0?3]/gbl inputs 18 17 irqx inputs because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 25 2.5.5.2 clkin to clkout skew table 17 describes the clkout- to- clkin skew timing. for designs that use the clkout synchronization mode, use the skew values listed in table 16 to adjust the rise-to-fall timing values specified for clkin synchronization. figure 12 shows the relationship between the clkout and clkin timings. 2.5.5.3 dma data transfers table 17 describes the dma signal timing. the dreq signal is synchronized with refclk . to achieve fast response, a synchr onized peripheral should assert dreq according to the timings in tabl e 17 . figure 13 shows synchronous peripheral interaction. table 16. clkout skew no. characteristic min 1 max 1 units 20 rise-to-rise skew 0.0 0.95 ns 21 fall-to-fall skew ?1.5 1.0 ns 23 clkout phase (1.1 v, 133 mhz) ? phase high ? phase low 2.2 2.2 ? ? ns ns 24 clkout phase (1.1 v, 100 mhz) ? phase high ? phase low 3.3 3.3 ? ? ns ns notes: 1. a positive number indicates that clkout precedes clkin, a negative number indicates that clkout follows clkin. 2. skews are measured in clock mode 29, with a clkin:clkout ratio of 1:1. the same skew is valid for all clock modes. 3. clkout skews are measured using a load of 10 pf. 4. clkout skews and phase are not measured for 500/166 mh z parts because these parts only use clkin mode. figure 12. clkout and clkin signals. table 17. dma signals no. characteristic ref = clkin units min max 37 dreq set-up time before the 50% level of the falling edge of refclk 5.0 ? ns 38 dreq hold time after the 50% level of the falling edge of refclk 0.5 ? ns 39 done set-up time before the 50% level of the rising edge of refclk 5.0 ? ns 40 done hold time after the 50% level of the rising edge of refclk 0.5 ? ns 41 dack /drack /done delay after the 50% level of the refclk rising edge 0.5 7.5 ns clkin clkout 20 21 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 26 2.5.6 dsi timing the timings in the following sections are based on a 20 pf capacitive load. 2.5.6.1 dsi asynchronous mode figure 13. dma signals table 18. dsi asynchronous mode timing no. characteristics min max unit 100 attributes 1 set-up time before strobe (hwbs[n] ) assertion 1.5 ? ns 101 attributes 1 hold time after data strobe deassertion 1.3 ? ns 102 read/write data strobe deassertion width: ? dcr[htaad] = 1 ? consecutive access to the same dsi ? different device with dcr[htadt] = 01 ? different device with dcr[htadt] = 10 ? different device with dcr[htadt] = 11 ? dcr[htaad] = 0 1.8 + t refclk 5 + t refclk 5 + (1.5 t refclk ) 5 + (2.5 t refclk ) 1.8 + t refclk ? ns ns ns ns ns 103 read data strobe deassertion to output data high impedance ? 8.5 ns 104 read data strobe assertion to output data active from high impedance 2.0 ? ns 105 output data hold time after read data strobe deassertion 2.2 ? ns 106 read/write data strobe assertion to hta active from high impedance 2.2 ? ns 107 output data valid to hta assertion 3.2 ? ns 108 read/write data strobe assertion to hta valid 2 ?7 . 4n s 109 read/write data strobe deassertion to output hta high impedance. (dcr[htaad] = 0, hta at end of access released at logic 0) ?6 . 5n s 110 read/write data strobe deassertion to output hta deassertion. (dcr[htaad] = 1, hta at end of access released at logic 1) ?6 . 5n s 111 read/write data strobe deassertion to output hta high impedance. (dcr[htaad] = 1, hta at end of access released at logic 1 ? dcr[htadt] = 01 ? dcr[htadt] = 10 ? dcr[htadt] = 11 ? 5 + t refclk 5 + (1.5 t refclk ) 5 + (2.5 t refclk ) ns ns ns 112 read/write data strobe assertion width 1.8 + t refclk ?n s 201 host data input set-up time before write data strobe deassertion 1.0 ? ns 202 host data input hold time after write data strobe deassertion 1.7 ? ns notes: 1. attributes refers to the following signals: hcs , ha[11?29], hcid[0?4], hdst, hrw, hrds , and hwbsn . 2. this specification is tested in dual-strobe mode. timing in single -strobe mode is guaranteed by design. 3. all values listed in this tabl e are tested or guaranteed by design. refclk dreq done dack /done /drack 37 38 40 39 41 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 27 figure 14 shows dsi asynchronous read signals timing. figure 14. asynchronous single- and dual-strobe modes read timing diagram hdbsn 1 ha[11?29] hcs hd[0?63] 102 100 105 101 103 104 109 108 106 hta 4 hcid[0?4] hdst hta 3 107 110 111 112 hrw 1 hwbsn 2 hrds 2 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. 3. hta released at logic 0 (dcr[htaad] = 0) at end of access; used with pull-down implementation. 4. hta released at logic 1 (dcr[htaad] = 1) at end of access; used with pull-up implementation. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 28 figure 15 shows dsi asynchronous write signals timing. figure 16 shows dsi asynchronous broadcast write signals timing. figure 15. asynchronous single- and dual-strobe modes write timing diagram figure 16. asynchronous broadcast write timing diagram hd[0?63] 100 101 102 201 202 109 106 hwbsn 2 108 110 111 112 hdbsn 1 hta 4 hta 3 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. 3. hta released at logic 0 (dcr[htaad] = 0) at end of access; used with pull-down implementation. 4. hta released at logic 1 (dcr[htaad] = 1) at end of access; used with pull-up implementation. ha[11?29] hcs hcid[0?4] hdst hrw 1 hrds 2 hd[0?63] 100 101 102 201 202 hwbsn 2 112 hdbsn 1 notes: 1. used for single-strobe mode access. 2. used for dual-strobe mode access. ha[11?29] hcs hcid[0?4] hdst hrw 1 hrds 2 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 29 2.5.6.2 dsi synchronous mode table 19. dsi inputs in synchronous mode no. characteristic expression 1.1 v core units min max 120 hclkin cycle time 1,2 htc 10.0 55.6 ns 121 hclkin high pulse width (0.5 0.1) htc 4.0 33.3 ns 122 hclkin low pulse width (0.5 0.1) htc 4.0 33.3 ns 123 ha[11?29] inputs set-up time ? 1.2 ? ns 124 hd[0?63] inputs set-up time ? 0.6 ? ns 125 hcid[0?4] inputs set-up time ? 1.3 ? ns 126 all other inputs set-up time ? 1.2 ? ns 127 all inputs hold time ? 1.5 ? ns notes: 1. values are based on a frequency range of 18?100 mhz. 2. refer to table 7 for hclkin frequency limits. table 20. dsi outputs in synchronous mode no. characteristic 1.1 v core units min max 128 hclkin high to hd[0?63] output active 2.0 ? ns 129 hclkin high to hd[0?63] output valid ? 7.6 ns 130 hd[0?63] output hold time 1.7 ? ns 131 hclkin high to hd[0?63] output high impedance ? 8.3 ns 132 hclkin high to hta output active 2.2 ? ns 133 hclkin high to hta output valid ? 7.4 ns 134 hta output hold time 1.7 ? ns 135 hclkin high to hta high impedance ? 7.5 ns because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 electrical characteristics freescale semiconductor 30 2.5.7 tdm timing figure 17. dsi synchronous mode signals timing diagram table 21. tdm timing no. characteristic expression 1.1 v core units min max 300 tdmxrclk/tdmxtclk tc 1 16 ? ns 301 tdmxrclk/tdmxtclk high pulse width (0.5 0.1) tc 7 ? ns 302 tdmxrclk/tdmxtclk low pulse width (0.5 0.1) tc 7 ? ns 303 tdm receive all input set-up time 1.3 ? ns 304 tdm receive all input hold time 1.0 ? ns 305 tdmxtclk high to tdmxtdat/tdmxrclk output active 2,3 2.8 ? ns 306 tdmxtclk high to tdmxtdat/tdmxrclk output ? 10.0 ns 307 all output hold time 4 2.5 ? ns 308 tdmxtclk high to tdmxtdat/tdmxrclk output high impedance 2,3 ? 10.7 ns 309 tdmxtclk high to tdmxtsyn output valid 2 ?9.7ns 310 tdmxtsyn output hold time 4 2.5 ? ns notes: 1. values are based on a a maximum frequency of 62.5 mhz. the tdm interface supports any frequency below 62.5 mhz. devices operating at 300 mhz are limited to a maximum tdmxrclk/tdmxtclk frequency of 50 mhz. 2. values are based on 20 pf capacitive load. 3. when configured as an output, tdmxrclk acts as a second data link. see the msc8113 reference manual for details. 4. values are based on 10 pf capacitive load. hclkin ha[11?29] input signals all other input signals hd[0?63] output signals hta output signal ~ ~ hd[0?63] input signals 120 127 123 126 127 122 121 131 130 129 128 133 135 134 132 ~ ~ ~ ~ hcid[0?4] input signals 125 127 127 124 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
electrical characteristics msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 31 figure 18. tdm inputs signals figure 19. tdm output signals tdmxrclk tdmxrdat tdmxrsyn 300 301 302 303 303 304 304 tdmxtclk tdmxtdat ~ ~ tdmxtsyn ~ ~ 305 306 308 307 300 301 302 310 309 tdmxrclk because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 32 2.5.8 uart timing 2.5.9 timer timing table 22. uart timing no. characteristics expression min max un it 400 urxd and utxd inputs high/low duration 16 t refclk 160.0 ? ns 401 urxd and utxd inputs rise/fall time 10 ns 402 utxd output rise/fall time 10 ns figure 20. uart input timing figure 21. uart output timing table 23. timer timing no. characteristics ref = clkin unit min max 500 timerx frequency 10.0 ? ns 501 timerx input high period 4.0 ? ns 502 timerx output low period 4.0 ? ns 503 timerx propagations delay from its clock input 3.1 9.5 ns utxd, urxd 400 inputs 400 401 401 utxd output 402 402 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 33 2.5.10 ethernet timing 2.5.10.1 management interface timing figure 22. timer timing table 24. ethernet controller management interface timing no. characteristics min max unit 801 ethmdio to ethmdc rising edge set-up time 10 ? ns 802 ethmdc rising edge to ethmdio hold time 10 ? ns figure 23. mdio timing relationship to mdc 500 502 501 timerx (input) timerx (output) 503 valid ethmdc ethmdio 802 801 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 34 2.5.10.2 mii mode timing 2.5.10.3 rmii mode table 25. mii mode signal timing no. characteristics min max unit 803 ethrx_dv, ethrxd[0?3], ethrx_er to ethrx_clk rising edge set-up time 3.5 ? ns 804 ethrx_clk rising edge to ethrx_dv, ethrxd[0?3], ethrx_er hold time 3.5 ? ns 805 ethtx_clk to ethtx_en, ethtxd[0?3], ethtx_er output delay 1 14.6 ns figure 24. mii mode signal timing table 26. rmii mode signal timing no. characteristics 1.1 v core unit min max 806 ethtx_en,ethrxd[0?1], ethcrs_dv, ethrx_er to ethref_clk rising edge set-up time 1.6 ? ns 807 ethref_clk rising edge to ethrxd[0?1], ethcrs_dv, ethrx_er hold time 1.6 ? ns 811 ethref_clk rising edge to ethtxd[0?1], ethtx_en output delay. 3 12.5 ns figure 25. rmii mode signal timing valid ethrx_clk ethrx_dv ethrxd[0?3] ethtx_clk ethrx_er ethtx_en ethtxd[0?3] valid valid ethtx_er 803 804 805 valid ethref_clk ethcrs_dv ethrxd[0?1] ethrx_er 807 806 ethtx_en ethtxd[0?1] valid valid 811 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 35 2.5.10.4 smii mode 2.5.11 gpio timing table 27. smii mode signal timing no. characteristics min max unit 808 ethsync_in, ethrxd to ethclock rising edge set-up time 1.0 ? ns 809 ethclock rising edge to ethsync_in, ethrxd hold time 1.0 ? ns 810 ethclock rising edge to ethsync, ethtxd output delay 1.5 1 6.0 2 ns notes: 1. measured using a 5 pf load. 2. measured using a 15 pf load. figure 26. smii mode signal timing table 28. gpio timing no. characteristics ref = clkin unit min max 601 refclk edge to gpio out valid (gpio out delay time) ? 6.1 ns 602 refclk edge to gpio out not valid (gpio out hold time) 1.1 ? ns 603 refclk edge to high impedance on gpio out ? 5.4 ns 604 gpio in valid to refclk edge (gpio in set-up time) 3.5 ? ns 605 refclk edge to gpio in not valid (gpio in hold time) 0.5 ? ns figure 27. gpio timing valid ethclock ethsync_in ethrxd ethsync ethtxd valid valid 810 809 808 refclk gpio (output) gpio (input) valid 603 high impedance 604 605 602 60 1 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 36 2.5.12 ee signals figure 28 shows the signal behavior of the ee pins. 2.5.13 jtag signals table 29. ee pin timing number characteristics type min 65 ee0 (input) asynchronous 4 core clock periods 66 ee1 (output) synchronous to core clock 1 core clock period notes: 1. the core clock is the sc140 core clock. the ratio between t he core clock and clkout is configured during power-on-reset. 2. refer to table 1-4 on page 1-6 for details on ee pin functionality. figure 28. ee pin timing table 30. jtag timing no. characteristics all frequencies unit min max 700 tck frequency of operation (1/(t c 4); maximum 25 mhz) 0.0 25 mhz 701 tck cycle time 40.0 ? ns 702 tck clock pulse width measured at v m = 1.6 v ?high ?low 20.0 16.0 ? ? ns ns 703 tck rise and fall times 0.0 3.0 ns 704 boundary scan input data set-up time 5.0 ? ns 705 boundary scan input data hold time 20.0 ? ns 706 tck low to output data valid 0.0 30.0 ns 707 tck low to output high impedance 0.0 30.0 ns 708 tms, tdi data set-up time 5.0 ? ns 709 tms, tdi data hold time 20.0 ? ns 710 tck low to tdo data valid 0.0 20.0 ns 711 tck low to tdo high impedance 0.0 20.0 ns 712 trst assert time 100.0 ? ns 713 trst set-up time to tck low 30.0 ? ns note: all timings apply to once module data transfers as well as any other transfers via the jtag port. ee1 out ee0 in 65 66 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 37 figure 29. test clock input timing diagram figure 30. boundary scan (jtag) timing diagram figure 31. test access port timing diagram figure 32. trst timing diagram tck (input) v m v m v ih v il 701 702 703 703 tck (input) data inputs data outputs data outputs v ih v il input data valid output data valid 705 704 706 707 tck (input) tdi (input) tdo (output) tdo (output) v ih v il input data valid output data valid tms 708 709 710 711 tck (input) trst (input) 713 712 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 hardware design considerations freescale semiconductor 38 3 hardware design considerations the following sections discuss areas to consider when the msc8113 device is designed into a system. 3.1 start-up sequencing recommendations use the following guidelines for start-up and power-down sequences: ?assert poreset and trst before applying power and keep the signals driven low until the power reaches the required minimum power levels. this can be implemented via weak pull-down resistors. ? clkin can be held low or allowed to toggle during the beginning of the power-up sequence. however, clkin must start toggling before the deassertion of poreset and after both power supplies have reached nominal voltage levels. ? if possible, bring up v dd / v ccsyn and v ddh together. if it is not possible, raise v dd / v ccsyn first and then bring up v ddh . v ddh should not exceed v dd / v ccsyn until v dd / v ccsyn reaches its nominal voltage level. similarly, bring both voltage levels down together. if that is not possible reverse the power-up sequence, with v ddh going down first and then v dd / v ccsyn . note: this recommended power sequencing for the msc8113 is different from the msc8102. external voltage applied to any inpu t line must not exceed the i/o supply v ddh by more than 0.8 v at any time, including during power-up. some designs require pull-up voltages applied to selected input lines during power-up for configuration purposes. this is an acceptable exception to the rule . however, each such input can draw up to 80 ma per input pin per device in the system during start-up. after power-up, v ddh must not exceed v dd / v ccsyn by more than 2.6 v. 3.2 power supply design considerations when implementing a new design, use the guidelines described in the msc8113 design checklist (an3374 for optimal system performance. msc8122 and msc8126 power circuit design recommendations and examples (an2937) provides detailed design information. figure 33 shows the recommended power decoupling circuit for th e core power supply. the voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. the voltage on the package pins should not drop below the minimum specified vo ltage level even for a very short spikes. this can be achieved by using the following guidelines: ? for the core supply, use a voltage regulator rated at 1.1 v with nominal rating of at least 3 a. this rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than supplies with lower current ratings. ? decouple the supply using low-esr capacitors mo unted as close as possible to the socket. figure 33 shows three capacitors in parallel to reduce the resistance. three capacitors is a recommended minimum number. if possible, mount at least one of the capacitors di rectly below the msc8113 device. figure 33. core power supply decoupling + - power supply or voltage regulator high frequency capacitors (very low esr and esl) bulk/tantalum capacitors with low esr and esl msc8113 maximum ir drop of 15 mv at 1 a note : use at least three capacitors. l max = 2 cm one 0.01 f capacitor for every 3 core supply (i min = 3 a) pads. 1.1 v each capacitor must be at least 150 f. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
hardware design considerations msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 39 each v cc and v dd pin on the msc8113 device should have a low-impeda nce path to the board power supply. similarly, each gnd pin should have a low-impedance path to the ground plane. the power supply pins drive distinct groups of logic on the chip. the v cc power supply should have at least four 0.1 f by-pass ca pacitors to ground located as closely as possible to the four sides of the package. the capacitor leads and as sociated printed circuit traces connecting to chip v cc , v dd , and gnd should be kept to less than half an inch per capacitor lead. a four -layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the msc8113 have fast rise and fall tim es. pcb trace interconnection length should be minimized to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pcb trace lengths of si x inches are recommended. for the dsi control signals in synchronous mode, ensure that the layout supports the dsi ac timing requirements and minimizes any signal crosstalk. capacitance calculations should consider all device loads as we ll as parasitic capacitances due to the pcb traces. attention to proper pcb layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the v cc , v dd , and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. there is one pair of pll supply pins: v ccsyn - gnd syn . to ensure internal clock stability, filter the power to the v ccsyn input with a circuit similar to the one in figure 34 . for optimal noise filtering, place the circuit as close as possible to v ccsyn . the 0.01-f capacitor should be closest to v ccsyn , followed by the 10-f capacitor, the 10-nh inductor, and finally the 10- resistor to v dd . these traces should be kept short and direct. provide an extremely low impedance path to the ground plane for gnd syn . bypass gnd syn to v ccsyn by a 0.01-f capacitor located as close as possible to the chip package. for best results, pl ace this capacitor on the backside of the pcb aligned with the depopulated void on the msc8113 located in the square defined by positions, l11, l12, l13, m11, m12, m13, n11, n12, and n13. 3.3 connectivity guidelines unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to v ddh or gnd , except for the following: ? if the dsi is unused (ddr[dsidis] is set), hcs and hbcs must pulled up and all the rest of the dsi signals can be disconnected. ? when the dsi uses synchronous mode, hta must be pulled up. in asynchronous mode, hta should be pulled either up or down, depending on design requirements. ? hdst can be disconnected if the dsi is in big-endian mode, or if the dsi is in little-endian mode and the dcr[dsrfa] bit is set. ? when the dsi is in 64-bit data bus mode and dcr[bem] is cleared, pull up hwbs[1?3] / hdbs[1?3] / hwbe[1?3] / hdbe[1?3] and hwbs[4?7] / hdbs[4?7] / hwbe[4?7] / hdbe[4?7] / pwe[4?7] / psddqm[4?7] / pbs[4?7] . ? when the dsi is in 32-bit data bus mode and dcr[bem] is cleared, hwbs[1?3] / hdbs[1?3] / hwbe[1?3] / hdbe[1?3] must be pulled up. ? when the dsi is in asynchronous mode, hbrst and hclkin should either be disconnected or pulled up. ? the following signals must be pulled up: hreset , sreset , artry , ta , tea , psdval , and aack . ? in single-master mode (bcr[ebm] = 0) with internal arbitration (ppc_acr[earb] = 0): ? bg , dbg , and ts can be left unconnected. ? ext_bg[2?3] , ext_dbg[2?3] , and gbl can be left unconnected if they are multiplexed to the system bus functionality. for any other functionality, connect the signal lines based on the multiplexed functionality. ? br must be pulled up. ? ext_br[2?3] must be pulled up if multiplexed to the system bus functionality. figure 34. v ccsyn bypass v dd 0.01 f 10 f v ccsyn 10 10nh because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 hardware design considerations freescale semiconductor 40 ? if there is an external bus master (bcr[ebm] = 1): ? br , bg , dbg , and ts must be pulled up. ? ext_br[2?3] , ext_bg[2?3] , and ext_dbg[2?3] must be pulled up if multiplexed to the system bus functionality. ? in single-master mode, abb and dbb can be selected as irq inputs and be connected to the non-active value. in other modes, they must be pulled up. note: the msc8113 does not support dll-enabled mode. for the following two clock schemes, ensure that the dll is disabled (that is, the dlldis bit in the hard reset configuration word is set). ? if no system synchronization is required (for example, the design does not use sdram), you can use any of the available clock modes. ?in the clkin synchronization mode, use the following connections: ? connect the oscillator output through a buffer to clkin . ? connect the clkin buffer output to the slave device (for example, sdram) making sure that the delay path between the clock buffer to the msc8113 and the sdram is equal (that is, has a skew less than 100 ps). ? valid clock modes in this scheme are: 0, 7, 15, 19, 21, 23, 28, 29, 30, and 31. note: see the clock chapter in the msc8113 reference manual for details. ? if the 60x-compatible system bus is not used and siumcr[pbse] is set, ppbs can be disconnected. otherwise, it should be pulled up. ? the following signals: swte, dsisync, dsi64, modck[1?2], cnfgs, chipid[0?3] , rstconf and bm[0?2] are used to configure the msc8113 and ar e sampled on the deassertion of the poreset signal. therefore, they should be tied to gnd or v ddh or through a pull-down or a pull-up resistor until the deassertion of the poreset signal. ? when they are used, int_out (if siumcr[intodc] is cleared), nmi_out , and irqxx (if not full drive) signals must be pulled up. ? when the ethernet controller is enabled and the smii mode is selected, gpio10 and gpio14 must not be connected externally to any signal line. note: for details on configuration, see the msc8113 user?s guide and msc8113 reference manual . for additional information, refer to the msc8113 design checklist (anxxxx). 3.4 external sdram selection the external bus speed implemented in a system determines the speed of the sdram used on that bus. however, because of differences in timing characteristics among various sdram manuf acturers, you may have use a faster speed rated sdram to assure efficient data transfer across the bus. for example, for 133 mhz operation, you may have to use 133 or 166 mhz sdram. always perform a detailed timing analysis using the msc8113 bus timing values and the manufacturer specifications for the sdram to ensure correct operation within your system design. the output delay listed in sdram specifications is usually given for a load of 30 pf. scale the number to your specific board load using the typical scaling number provided by the sdram manufacturer. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
ordering information msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 41 3.5 thermal considerations an estimation of the chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (r ja p d ) eqn. 1 where t a = ambient temperature near the package ( c) r ja = junction-to-ambient thermal resistance ( c/w) p d = p int + p i/o = power dissipation in the package (w) p int = i dd v dd = internal power dissipation (w) p i/o = power dissipated from device on output pins (w) the power dissipation values for the msc8113 are listed in table 4 . the ambient temperature for the device is the air temperature in the immediate vicinity th at would cool the device. the junction-to -ambient thermal resistances are jedec standard values that provide a quick and easy estimation of th ermal performance. there are two values in common usage: the value determined on a single layer board and the value obtain ed on a board with two planes. the value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (pcb). the value obtained using a single layer board is appropriate fo r tightly packed pcb configuratio ns. the value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 w/cm 2 with natural convection) and well separated components. based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. if t j appears to be too high, either lower the ambient temperature or the power dissipation of the chip. you can verify the juncti on temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. the msc8113 device case surface is too shiny (low emissiv ity) to yield an accurate infrared temperature measurement. use the following equation to determine t j : t j = t t + ( ja p d ) eqn. 2 where t t = thermocouple (or infrared) temp erature on top of the package ( c) ja = thermal characterization parameter ( c/w) p d = power dissipation in the package (w) note: see msc8102, msc8122, and msc8126 thermal management design guidelines (an2601/d). 4 ordering information consult a freescale semiconductor sales office or authorized dist ributor to determine product availability and place an order. part package type core voltage operating temperature core frequency (mhz) order number lead-free lead-bearing msc8113 flip chip plastic ball grid array (fc-pbga) 1.1 v ?40 to 105c 300 msc8113tvt3600v MSC8113TMP3600V 400 msc8113tvt4800v msc8113tmp4800v because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
msc8113 tri-core digital signal processor data sheet, rev. 1 package information freescale semiconductor 42 5 package information 6 product documentation ? msc8113 technical data sheet (msc8113). details the signals, ac/dc characteristics, clock signal characteristics, package and pinout, and electrical design considerations of the msc8113 device. ? msc8113 reference manual (msc8113rm). includes functional descrip tions of the extended cores and all the internal subsystems including configuration and programming information. ? application notes . cover various programming topics related to the starcore dsp core and the msc8113 device. ? sc140 dsp core reference manual . covers the sc140 core architecture, control registers, clock registers, program control, and instruction set. figure 35. msc8113 mechanical information, 431-pin fc-pbga package notes: 1. all dimensions in millimeters. 2. dimensioning and tolerancing per asme y14.5m?1994. 3. features are symmetrical abou t the package center lines unless dimensioned otherwise. 4. maximum solder ball diameter measured parallel to datum a. 5. datum a, the seating plane, is determined by the spherical crowns of the solder balls. 6. parallelism measurement shall exclude any effect of mark on top surface of package. 7. capacitors may not be present on all devices. 8. caution must be taken not to short capacitors or exposed metal capacitor pads on package top. 9. fc cbga (ceramic) package code: 5238. fc pbga (plastic) package code: 5263. 10.pin 1 indicator can be in the form of number 1 marking or an ?l? shape marking. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
revision history msc8113 tri-core digital signal processor data sheet, rev. 1 freescale semiconductor 43 7 revision history table 31 provides a revision history for this data sheet. table 31. document revision history revision date description 0 may 2008 ? initial public release. 1 dec. 2008 ?added figure 8 and associated text that was omitted from the previous revision on p. 17. ? clarified the wording of note 2 in ta ble 1 5 on p. 23. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x
document number: msc8113 rev. 1 12/2008 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be va lidated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale?, the freescale logo, codewarrior, and starcore are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2008. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-m eguro, meguro-ku tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 010 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 +1-800 441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: msc711x

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